MTU Library Catalogue

Syndetics cover image
Image from Syndetics

Fundamentals of logic design / Charles H. Roth.

By: Roth, Charles H.
Material type: materialTypeLabelBookPublisher: St Paul, MN : West Publ., 1992Edition: 4th ed.Description: xviii, 770 p. : ill. ; 27 cm. + hbk.ISBN: 0314922180.Subject(s): Logic circuits | Logic designDDC classification: 621.395
Contents:
Introduction Number systems and conversion -- Boolean algebra -- Boolean algebra (continued) -- Algebraic simplification -- Applications of boolean algebra -- Karnaugh maps -- Quine-McCluskey method -- Multi-level gate networks NAND and NOR gates -- Multiple-output networks Multiplexers, decoders, read-only memories and programmable logic arrays -- Combinational network design -- Flip-flops -- Counters and similar sequential networks -- Analysis of clocked sequential networks -- Derivation of state graphs and tables -- Reduction of state tables State assignment -- Sequential network design -- Iterative networks -- MSI integrated circuits in sequential network design -- Sequential network design with programmable logic devices (PLDs) -- Networks for addition and subtraction -- Networks for arithmetic operations -- State machine design with SM charts -- Analysis of asynchronous sequential networks -- Derivation and reduction of primitive flow tables -- State assignment and realization of flow tables -- Hazards -- Asynchronous sequential network design.
Holdings
Item type Current library Call number Copy number Status Barcode
General lending MTU Bishopstown Library Lending 621.395 (Browse shelf(Opens below)) 1 Available 00073760
Total holds: 0

Previous ed.: 1985.

Includes bibliographical references (pages 723-725) and index.

Introduction Number systems and conversion -- Boolean algebra -- Boolean algebra (continued) -- Algebraic simplification -- Applications of boolean algebra -- Karnaugh maps -- Quine-McCluskey method -- Multi-level gate networks NAND and NOR gates -- Multiple-output networks Multiplexers, decoders, read-only memories and programmable logic arrays -- Combinational network design -- Flip-flops -- Counters and similar sequential networks -- Analysis of clocked sequential networks -- Derivation of state graphs and tables -- Reduction of state tables State assignment -- Sequential network design -- Iterative networks -- MSI integrated circuits in sequential network design -- Sequential network design with programmable logic devices (PLDs) -- Networks for addition and subtraction -- Networks for arithmetic operations -- State machine design with SM charts -- Analysis of asynchronous sequential networks -- Derivation and reduction of primitive flow tables -- State assignment and realization of flow tables -- Hazards -- Asynchronous sequential network design.